1. Field of the Invention
The present invention relates to processes for forming local interconnects and polysilicon resistors on MOS devices. More particularly, the present invention relates to processes of forming local interconnects and polysilicon resistors by reacting cobalt with polysilicon.
2. The Prior Art
High performance ULSI microprocessors require large capacity, on chip SRAM while following the standard technology shrink path from previous generation devices. Polysilicon resistor load four-transistor (4-T) SRAM cells are desirable since they provide the system with the density required for performance enhancement. However, a simplified local interconnect is necessary in order to keep the shrink path from one technology to the next. The local interconnect technique has been suggested as a means to reduce the SRAM cell area by reducing the number of contacts used for interconnects and to provide a reliable alternative method to the buried contact scheme.
Previous local interconnect schemes have concentrated around TiN processes in which the TiN was sputtered on or grown from TiSi.sub.2. Other techniques were based on PVD silicon films sputtered over titanium and the simultaneous formation of silicide and local interconnect structures. These techniques have not been reliable enough to be implemented in ULSI processes.
The use of TiN over TiSi.sub.2 has been suggested by Holloway et al. in U.S. Pat. No. 4,657,628 and by Tang et al. in U.S. Pat. No. 4,657,866. This technique, however, suffers from many processing problems which prevent the reliable manufacturing of these devices. TiN films which are grown from TiSi.sub.2 are very thin for patterning and low sheet resistance. TiN also suffers from the lack of etch selectivity to TiSi.sub.2 which makes it extremely hard to control subsequently dry and wet etch processes. Another shortcoming of this technique is the inability to strip the resist off the wafer without degrading the line width control of the TiN local interconnect strap. Hydrogen peroxide, which is used to strip the photoresist mask, can also severely attack the TiN layer.
Another technique has been suggested by Deveraux et al. in, "A New Device Interconnect Scheme For Sub-Micron VLSI," 84 IEDM pages 118-121. In this technique, a thin layer of refractory metal and amorphous silicon are deposited sequentially in the same pump down. The amorphous silicon is patterned and then the wafer is annealed whereby the refractory metal reacts with the amorphous silicon as well as single crystal silicon and polysilicon to form a silicide. The unreacted metal is then removed by wet etching.
This technique suffers from limitations such as oxidation of the titanium film during the silicon dry etch which contains oxygen species. Additionally, the photoresist stripping agent showed a tendency for attacking the refractory metal which in this case was titanium.
Polysilicon loads have been used in MOS devices for a substantial period of time. Published reports on polysilicon load processes have concentrated on two or more polysilicon layers used in conjunction with first layer polycided gate structures rather than salicided (both gate and drain) structures. A common process for forming polysilicon loads involves the following steps: gate oxide growth; deposition of polysilicon/tungsten gate material; patterning of polysilicon/tungsten gate; etching of polysilicon/tungsten gate; patterning and implantation of N+ source/drain/gate; poly 1/poly 2 dielectric deposition; patterning of polysilicon contact; deposition of a second layer of polysilicon; patterning and etching of polysilicon resistor; patterning and implantation of N+ contact. This technique does not allow the use of salicide processes which are essential for low sheet resistance of gate and source/drain regions for high performances systems. Although tungsten silicide gate material with low sheet resistance has been used extensively, the source/drain regions exhibited very high sheet resistance requiring expensive circuit solutions to get around this limitation in high performance systems.
In order to produce an acceptable contacting scheme between the second level polysilicon resistor and the first polysilicon gate or source/drain regions, it is necessary to solve the problems encountered with silicon to silicon or silicon to polysilicon interfaces. The native oxide films which are grown upon exposure of the substrate to ambient air can result in high contact resistance and process variations which significantly effect yields. Accordingly, the foregoing process was based on silicide free junctions in direct contact with the second polysilicon layer which is also free of silicide. This was followed by the resistor definition and contact patterning followed by doping implantation at the contact region to reduce the electrical resistance of the second layer of polysilicon contact.